题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
reg [7:0] cnt;
reg [3:0] cnt_e,cnt_o;
reg out;
always @ ( posedge clk_in or negedge rst )
begin
if(!rst)
begin
cnt<=8'd0;
end
else
begin
cnt<= (cnt==M_N-1) ? 8'd0 : cnt+8'd1;
end
end

        always @ ( posedge clk_in or negedge rst )
        begin
        if(!rst)
        begin
        cnt_e<=4'd0;
        cnt_e<=4'd0;
        end
        else if (cnt<c89)
        begin
        cnt_e<= (cnt_e==div_e-1) ? 4'd0: cnt_e+3'd1;
        cnt_o<=4'd0;
        end
        else
        begin
         cnt_o<= (cnt_o==div_o-1) ? 4'd0: cnt_o+3'd1;
         cnt_e<= 4'd0;
        end
        end

        always @ ( posedge clk_in or negedge rst )
            begin
            if(!rst)
            begin
            out<=1'b0;
            end
            else
            begin
            if(cnt<c89)
            begin
            out<=(cnt_e==0||cnt_e==(div_e/2) ) ? ~out: out;
            end
            else
            begin
             out<=(cnt_o==0||cnt_o==(div_o/2)) ? ~out: out;
            end
            end
            end

assign clk_out=out;
//*************code***********//
endmodule