题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg cnt2;
reg [2:0] cnt8;
reg [1:0] cnt4;
always @(posedge clk_in or negedge rst)
begin
if(!rst)
begin
cnt4=2'b01;
cnt8=3'b011;
cnt2=1'b0;
end
else
begin
cnt2=cnt2+1'b1;
cnt4=cnt4+2'b01;
cnt8=cnt8+3'b001;
end
end

assign clk_out2=cnt2;
assign clk_out4=cnt4[1];
assign clk_out8=cnt8[2];


//*************code***********//
endmodule