题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;

reg [2:0]state;

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
state<=s0;
end
else
begin
case(state)
s0 : state <= data ? s1 :s0;
s1 : state <= data ? s2 :s1;
s2 : state <= data ? s3 :s2;
s3 : state <= data ? s4 :s3;
s4 : state <= data ? s1 :s0;
endcase
end
end

always @ (*)
begin
if(!rst)
begin
flag=1'b0;
end
else 
begin
flag= state==s4;
end
end





//*************code***********//
endmodule