题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
// 01110001
reg [7:0] a_ray;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        a_ray <= 0;
        match <= 0;
    end
    else begin
        a_ray <= {a_ray[6:0],a};
        if (a_ray==8'b01110001) begin
            match <= 1;
        end
        else match <= 0;
    end
end
endmodule