题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module sub_mod(
input clk,
input rst_n,
input [7:0] in1,
input [7:0] in2,
output reg[7:0] c
);
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin 
	c<=0;
	end
		else
		begin
			if(in2>in1)
			begin
			c<=in1;
			end
			else
			begin
			c<=in2;
			end
		end
end

endmodule
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire [7:0]temp,temp1,out;
sub_mod ab(.c(temp),.in1(a),.in2(b),.clk(clk),.rst_n(rst_n)); 
sub_mod ac(.c(temp1),.in1(a),.in2(c),.clk(clk),.rst_n(rst_n));
sub_mod t(.c(out),.in1(temp),.in2(temp1),.clk(clk),.rst_n(rst_n));
assign d=out;
endmodule