题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

reg [3:0]   vld_d   ;
reg [7:0]   d_d     ;

always@(posedge clk or negedge rst) begin
    if(~rst)
        vld_d   <= 4'b0001;
    else
        vld_d   <= {vld_d[2:0], vld_d[3]};
end


always@(posedge clk or negedge rst) begin
    if(~rst) begin
        out <= 'd0;
        input_grant <= 1'b0;
        d_d <= 8'b0;
    end else if(vld_d[0]) begin
        d_d <= d;
        out <= d;
        input_grant <= 1'b1;
    end else if(vld_d[1]) begin
        out <= (d_d<<1) + d_d;
        input_grant <= 1'b0;
    end else if(vld_d[2]) begin
        out <= (d_d<<3) - d_d;
        input_grant <= 1'b0;
    end else if(vld_d[3]) begin
        out <= (d_d<<3);
        input_grant <= 1'b0;
    end
end

//*************code***********//
endmodule