题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire [7:0]e;
wire [7:0]f;
sub_mod uut(
.clk(clk),
.rst_n(rst_n),
.a(a),
.b(b),
.c(e)	
);
sub_mod uut1(
.clk(clk),
.rst_n(rst_n),
.a(a),
.b(c),
.c(f)	
);
sub_mod uut2(
.clk(clk),
.rst_n(rst_n),
.a(e),
.b(f),
.c(d)	
);
endmodule


module sub_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	output [7:0]c	
);
reg [8:0]c_reg = 8'd0;
assign c = c_reg;

always @(posedge rst_n)
begin
	c_reg <= 8'd0;
end
always @(posedge clk)
begin
	if(a>b)
	begin
		c_reg <= b;
	end
	else if(b>a)
	begin
		c_reg <= a;
	end
	else if(b==a)
	begin
		c_reg <= b;
	end
end
endmodule