题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
reg [7:0]data_lock;
reg [1:0]cnt;

always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt<=0;
else if(valid_in)begin//这儿一定是valid_in才能计数 把他放进去
if(cnt==2)
cnt<=0;
else
cnt<=cnt+1; 
end
end

always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_lock<=0;
else if(valid_in)
data_lock<=data_in;
// else
// data_lock<=data_lock;
end

always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
valid_out<=0;
data_out<=0;end
else if(cnt==2'b01&&valid_in)begin
valid_out<=1;
data_out<={data_lock,data_in[7:4]};
end
else if(cnt==2'b10&&valid_in)begin
valid_out<=1;
data_out<={data_lock[3:0],data_in};
end
else begin
valid_out<=0;
data_out<=data_out;end

end
endmodule