题解 | #自动贩售机1#

注意：

1、注意要使用状态机，确认有哪几个状态；

2、注意几个状态相同时next_stata写法；

3、注意输出out1和out2改变的时刻。

4、注意下面的默认状态，既没有d1,d2,d3输入时，next_stata的取值，不能是S0。

S0: next_stata <= d1? S0_5: d2? S1: d3? S2: next_stata;

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
	
	parameter S0=0, S0_5=1, S1=2, S1_5=3, S2=4, S2_5=5, S3=6;
	reg [2:0] cur_stata, next_stata;
	
	always@(posedge clk or negedge rst)begin
		if(~rst)begin
			cur_stata <= S0;
		end
		else 
			cur_stata <= next_stata;
	end
	always@(*)
		case(cur_stata)
			S0: next_stata <= d1? S0_5: d2? S1: d3? S2: next_stata;
			S0_5: next_stata <= d1? S1: d2? S1_5: d3? S2_5: next_stata;
			S1: next_stata <= d1? S1_5: d2? S2: d3? S3: next_stata;
			S1_5,
			S2,
			S2_5,
			S3: next_stata <= S0;
			default: next_stata <= S0;
		endcase
			
	always@(*)begin
		if(~rst)begin
			out1 <= 0;
			out2 <= 0;
		end
		else begin
			case(cur_stata)
				S1_5: begin out1 <= 1; out2 <= 0;end
				S2: begin out1 <= 1; out2 <= 1;end
				S2_5: begin out1 <= 1; out2 <= 2;end
				S3: begin out1 <= 1; out2 <= 3;end
				default: begin out1 <= 0; out2 <= 0;end
			endcase
		end
	end

	
//*************code***********//
endmodule