题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5,s6=3'd6;
reg [2:0] state,next;
reg [2:0] counter;

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		state<=s0;
	end
	else begin
		state<=next;
	end
end

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		counter<=3'd0;
	end
	else begin 
		if(counter==3'd5) begin
			counter<=3'd0;
		end
		else begin
			counter<=3'd1+counter;
		end
	end
end



always @ (*) begin
	case (state) 
		s0:next<=data?s6:s1;
		s1:next<=data?s2:s6;
		s2:next<=data?s3:s6;
		s3:next<=data?s4:s6;
		s4:next<=data?s6:s5;
		s5:next<=s0;
		s6:next<=(counter==3'd5)?s0:s6;
	endcase
end

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		match<=1'd0;
		not_match<=1'd0;
	end
	else begin
		if(state==s5 & data==0) begin
			match<=1'd1;
			not_match<=1'd0;
		end
		else begin
			if(counter==3'd5 & state==s6) begin
				match<=1'd0;
				not_match<=1'd1;
			end
			else begin
				match<=1'd0;
				not_match<=1'd0;
			end
		end
	end
end

endmodule