题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

parameter idle=4'd0, A=4'd1, b=4'd2, c=4'd3, d=4'd4, e=4'd5, f=4'd6, g=4'd7, h=4'd8;
reg [3:0] state,next;

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		state<=idle;
	end
	else begin
		state<=next;
	end
end

always @ (*) begin
	case(state)
	4'd0: next = a? idle:A;
	4'd1: next = a? b:A;
	4'd2: next = a? c:A;
	4'd3: next = a? d:A;
	4'd4: next = a? idle:e;
	4'd5: next = a? b:f;
	4'd6: next = a? b:g;
	4'd7: next = a? h:A;
	4'd8: next = a? c:A;
	default: next = idle;
	endcase
end

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		match <= 0;
	end
	else begin
		match <= state==h;
	end
end
  
endmodule