题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg b;
always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		b <= 0;
	end
	else begin
		b <= a;
	end
end

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		rise<=1'b0;
		down<=1'b0;
	end
	else begin
		if((b==1'b0)&(a==1'b1)) begin
			rise<=1'b1;
			down<=1'b0;
		end
		else begin
			if((b==1'b1) & (a==1'b0)) begin
				rise<=1'b0;
				down<=1'b1;
			end
			else begin
				rise<=1'b0;
				down<=1'b0;
			end
		end
	end
end

	
endmodule