题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

reg a,b;

always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        a <= 0;
        b <= 0;
    end
    else begin
        a <= ~C&a | C&~b;
        b <= ~C&a | C&b;
    end
end

assign Y = ~C&b&a | C&b;

endmodule