题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	
reg [1:0]a_buf=0;
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		a_buf <= 0;
	else
		a_buf <= {a_buf[0],a};
end

always@(*)begin
	if(a_buf==2'b01)begin
		rise=1;
		down=0;
	end else if(a_buf==2'b10)begin	
		rise=0;
		down=1;
	end else begin
		rise=0;
		down=0;
	end
end

endmodule