题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
	reg [3:0] d_r;
	reg [2:0] cnt;
	reg valid;

	always @(posedge clk or negedge rst) begin
		if(rst == 1'b0)
			cnt <= 3'd0;
		else if(cnt == 3'd3)
			cnt <= 3'd0;
		else
			cnt <= cnt + 1'b1;			
	end

	always @(posedge clk or negedge rst) begin
		if(rst == 1'd0)
			d_r <= 4'd0;
		else if(cnt == 3'd3)
			d_r <= d;
		else
			d_r <= {d_r[2:0],d_r[3]};
	end

	always @(posedge clk or negedge rst) begin
		if(rst == 1'b0)
			valid <= 1'b0;
		else if(cnt == 3'd3)
			valid <= 1'b1;
		else
			valid <= 1'b0;
	end

	assign dout = d_r[3];
	assign valid_in = valid;

//*************code***********//

endmodule