题解 | #边沿检测#

这样会漏掉在一个周期内有上升和下降的信号，不过说a缓慢变化，那就可以忽略这种信号了

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg a_temp;
always @(posedge clk or negedge rst_n)
begin
	if (!rst_n)
	a_temp <= 0;
	else
	a_temp <= a;
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin rise <= 0; down <= 0; end
	else if (~a_temp & a)
	begin rise <= 1; down <= 0; end
	else if (a_temp & ~a)
	begin down <= 1; rise <=0; end
	else 
	begin rise <= 0; down <= 0; end
end


endmodule