题解1 | #根据状态转移图实现时序电路#

状态机还是好写的

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);


// USE FSM 

reg [1:0] curr_state;
reg [1:0] nxt_state;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
    curr_state <= 2'b00;
    else 
    curr_state <= nxt_state;
end

always @(*)(1444584)
begin
    case(curr_state)
    2'b00: nxt_state = C? 2'b01: 2'b00;
    2'b01: nxt_state = C? 2'b01: 2'b11;
    2'b11: nxt_state = C? 2'b10: 2'b11;
    2'b10: nxt_state = C? 2'b10: 2'b00;
    default: nxt_state = 2'b00;
    endcase
end

assign Y = (curr_state[1] & curr_state[0])|
            (C & curr_state[1] & ~curr_state[0]);
endmodule