题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********// moore

	parameter IDEL=0, S0=1, S1=2, S2=3, S3=4, S4=5, S5=6;
	reg [2:0] cstate, nstate;

	always@(posedge clk or negedge rst) begin
		if(!rst) begin
			cstate <= IDEL;
		end
		else begin
			cstate <= nstate;
		end
	end

	always@(*) begin
		case(cstate)
			IDEL:   nstate = d1?S0:(d2?S1:(d3?S3:nstate));
			S0:		nstate = d1?S1:(d2?S2:(d3?S4:nstate));
			S1:		nstate = d1?S2:(d2?S3:(d3?S5:nstate));
			S2,		
			S3,		
			S4,		
			S5:		nstate = d1?S0:(d2?S1:(d3?S3:IDEL));
			default:nstate = IDEL;
		endcase
	end

	always@(posedge clk or negedge rst) begin
		if(!rst) begin
			out1 <= 1'b0;
			out2 <= 2'd0;
		end
		else begin
			case(nstate)
				S2: begin
					out1 <= 1'b1;
					out2 <= 2'd0;
				end
				S3: begin
					out1 <= 1'b1;
					out2 <= 2'd1;
				end
				S4: begin
					out1 <= 1'b1;
					out2 <= 2'd2;
				end
				S5: begin
					out1 <= 1'b1;
					out2 <= 2'd3;
				end
				default: begin
					out1 <= 1'b0;
					out2 <= 2'd0;
				end
			endcase
		end
	end

//*************code***********//
endmodule