题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
	reg [1:0] cnt;
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt <= 'd0;
		end
		else begin
			cnt <= valid_in?((cnt=='d2)?'d0:(cnt+'d1)):cnt;
		end
	end
	reg [7:0] data_reg;
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_reg <= 'd0;
		end
		else begin
			data_reg <= valid_in?data_in:data_reg;
		end
	end
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_out <= 'd0;
			valid_out <= 1'b0;
		end
		else begin
			case(cnt)
				2'd1: begin
					data_out <= valid_in?{data_reg,data_in[7:4]}:data_out;
					valid_out <= valid_in?1'b1:1'b0;
				end
				2'd2: begin
					data_out <= valid_in?{data_reg[3:0],data_in}:data_out;
					valid_out <= valid_in?1'b1:1'b0;
				end
				default: begin
					data_out <= data_out;
					valid_out <= 1'b0;
				end
			endcase
		end
	end
endmodule