题解 | #数据串转并电路#
数据串转并电路
https://www.nowcoder.com/practice/6134dc3c8d0741d08eb522542913583d
1、自己写的，比较乱；感觉自己需要进行总结了，重新刷HDLBits时序电路的部分，感觉自己现在思维已经模糊了。意识不清。
2、是先到的放在低位。
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [5:0] seq_6, cnt;
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
seq_6 <= 0;
end
else if (valid_a && ready_a) begin
seq_6 <= {data_a, seq_6[5:1]};
end
end
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
cnt <= 0;
end
else if (valid_a && ready_a) begin
cnt <= cnt == 5 ? 0 : cnt + 1;
end
end
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
valid_b <= 0;
end
else if (cnt == 5) begin
valid_b <=1;
end
else begin
valid_b <=0;
end
end
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
data_b <= 0;
ready_a = 1'b0;
end
else if (cnt == 5) begin
data_b <= {data_a, seq_6[5:1]};
ready_a = 1'b1;
end
else begin
data_b <= data_b;
ready_a = 1'b1;
end
end
endmodule
reg [5:0] data_reg;
reg [2:0] data_cnt;
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
ready_a <= 'd0;
else
ready_a <= 1'd1;
end
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
data_cnt <= 'd0;
else if(valid_a && ready_a)
data_cnt <= (data_cnt == 3'd5) ? 'd0 : (data_cnt + 1'd1);
end
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
data_reg <= 'd0;
else if(valid_a && ready_a)
data_reg <= {data_a, data_reg[5:1]};
end
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)begin
valid_b <= 'd0;
data_b <= 'd0;
end
else if(data_cnt == 3'd5)begin
valid_b <= 1'd1;
data_b <= {data_a, data_reg[5:1]};
end
else
valid_b <= 'd0;
end
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