题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
    parameter Cycle_out = 87;
    parameter Cycle_in1 = 8;
    parameter Cycle_in2 = 9;
    parameter Switch = 24;
    reg [6:0] cnt_out;
    reg [3:0] cnt_in;
    always@(posedge clk_in or negedge rst) begin
        if(!rst) begin
            cnt_out <= 'd0;
        end
        else begin
            cnt_out <= (cnt_out==Cycle_out-'d1)?'d0:(cnt_out+'d1);
        end
    end
    always@(posedge clk_in or negedge rst) begin
        if(!rst) begin
            cnt_in <= 'd0;
        end
        else begin
            if(cnt_out<=Switch-'d1)
                cnt_in <= (cnt_in==Cycle_in1-'d1)?'d0:(cnt_in+'d1);
            else begin
                    cnt_in <= (cnt_in==Cycle_in2-'d1)?'d0:(cnt_in+'d1);
            end
        end
    end
    reg clk_out_r;
    always@(posedge clk_in or negedge rst) begin
        if(!rst) begin
            clk_out_r <= 1'b0;
        end
        else begin
            clk_out_r <= (cnt_in<='d3);
        end
    end
    assign clk_out = clk_out_r;
endmodule