题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
    parameter S0 = 2'd0; // 没有有效数据
    parameter S1 = 2'd1; // 有一个有效数据，但不足以输出
    parameter S2 = 2'd2; // 有两个有效数据，够一次输出
    reg [7:0] data_reg;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            data_reg <= 'd0;
        end
        else begin
            data_reg <= valid_in?data_in:data_reg;
        end
    end
    reg [1:0] cstate, nstate;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cstate <= S0;
        end
        else begin
            cstate <= nstate;
        end
    end
    always@(*) begin
        case(cstate)
            S0: begin
                nstate = valid_in?S1:S0;
            end
            S1: begin
                nstate = valid_in?S2:S1;
            end
            S2: begin
                nstate = valid_in?S0:S2;
            end
            default: begin
                nstate = S0;
            end
        endcase
    end
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            data_out <= 'd0;
            valid_out <= 1'b0;
        end
        else begin
            case(cstate)
                S0: begin
                    data_out <= data_out;
                    valid_out <= 1'b0;
                end
                S1: begin
                    data_out <= valid_in?{data_reg,data_in[7:4]}:data_out;
                    valid_out <= valid_in?1'b1:1'b0;
                end
                S2: begin
                    data_out <= valid_in?{data_reg[3:0],data_in}:data_out;
                    valid_out <= valid_in?1'b1:1'b0;
                end
                default: begin
                    data_out <= 'd0;
                    valid_out <= 1'b0;
                end
            endcase
        end
    end
endmodule