题解 | #数据累加输出#

module valid_ready(
    input clk,   
	input rst_n,
	input [7:0]	data_in,
	input valid_a,
	input ready_b,
 	output ready_a,
 	output reg valid_b,
	output reg [9:0] data_out
);

    reg [1:0] num_cnt = 0;
    reg full_flag = 0;
    
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)begin
            num_cnt <= 2'd0;
            data_out <= 10'd0;
            full_flag <= 1'b0;
            valid_b <= 1'b0;
        end
        else begin
            if(valid_a == 1'b1 && ready_a == 1'b1)begin
                if(num_cnt == 2'd3 && full_flag == 1'b0)begin
                    full_flag <= 1'b1;
                    data_out <= data_out + data_in;
                    valid_b <= 1'b1;
                end
                else begin
                    valid_b <= 1'b0;
                    if(num_cnt == 2'd0)begin
                        num_cnt <= num_cnt + 1'b1;
                        data_out <= data_in;
                    end
                    else begin
                        num_cnt <= num_cnt + 1'b1;
                        data_out <= data_out + data_in;
                    end
                end
            end
        end
    end
    
    assign ready_a = (valid_b == 1 && ready_b == 0) ? 0 : 1;
    
    always@(*)begin
        if(valid_b == 1'b1)begin
            if(ready_b == 1'b1)begin
                num_cnt = 2'd0;
                full_flag = 1'b0;
            end
        end
    end

endmodule