题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output  reg flag
);
//*************code***********//
    reg [2:0] curr_state;
    reg [2:0] next_state;
    
    always @ (posedge clk or negedge rst)begin
        if (~rst) begin
            curr_state<=3'd0;
        end
        else
            curr_state<=next_state;
    end
    
    always @ (*)begin
        case (curr_state)
            3'd0:next_state<=(data)?3'd1:3'd0;
            3'd1:next_state<=(data)?3'd1:3'd2;
            3'd2:next_state<=(data)?3'd3:3'd0;
            3'd3:next_state<=(data)?3'd4:3'd0;
            3'd4:next_state<=(data)?3'd1:3'd2;

            default:next_state<=3'd0;
        endcase
    end
    always@(posedge clk or negedge rst) begin
        if(~rst)
            flag <= 0;
        else
            flag <= curr_state==3'd4;
    end    



//*************code***********//
endmodule