【开卷】第23期 MPS芯源2022数字IC笔试题

MPS芯源2022数字IC
时间2021.08.25

                           

1、Please code the divider by 3 with Verilog(50% duty cycle).用Verilog设计一个3分频器,要求50%占空比。

 

2、Please describe the digital P&R flow.请简述数字后端P&R流程。

 

3、Please use a MUX and INV to implement aXOR.如何用一个2选一的MUX和一个INV实现异或。

 

4、What are recovery and removal times?请描述recovery时间和removal时间的概念。

 

5、The clock cycle is T, the clock toregister output delay is Tco, setup and hold time of a register are Tsetup andThold, what's the Tdelay constrain?时钟周期为T,时钟到寄存器输出延时Tco,寄存器建立时间Tsetup,寄存器保持时间Thold。请描述逻辑延时Tdelay的建立和保持时间要求(不考虑时钟延时)。

 

6、What's the difference between a LATCH anda DFF?请描述LATCH和DFF的概念和区别?

 

7、What's the difference between asynchronous and an asynchronous circuit?同步电路和异步电路的区别是什么?

 

8、What is IR-drop, in which area will beeasy to have IR-drop problem ?什么是IR-drop,在那些地方容易出IR-drop问题?

 

9、How do you synchronize an asynchronousinput?异步信号如何进行同步?

 

10、Please draw the state machine transmissiondiagram of the array detection 10010,code with Verilogand build the testbench and testcase to get 100% fsm coverage.画出可以检测10010序列的状态图,并用Verilog实现,搭建测试平台并写出可以达到100%状态机覆盖率的testcase。

 

11、What are gate-level simulations? You havea device that can be programmed via an 12C interface. What type of tests do yourecommend to run for gate level only?什么是门级仿真(后仿)?如果你有一个设备通过12C接口配置,有哪些针对门级仿真的测试用例?

 

12、Please constrain the timing of clock andinput signal in the waveform, both are input pins for a chip. 请对下图中的输入时钟和输入数据进行时序约束。



13、There is an X present in my gate-levelsimulation due to a timing violation. How do you identify the source of it andthe type of violation? 如果在后仿中波形中出现了X,如何去定位,且可能是什么问题?

 

14、Please describe the ECO flow(includingpre-mask ECO and post-mask ECO).请描述ECO流程,包括pre-mask和post-mask ECO。

 

15、What are various techniques to resolverouting congestion?如何解决routing congestion问题?

 

16、Please describe the rtl with INV, AND, OR andDFF. 请用与、或、非门和寄存器画出代码所描述的电路。

always@(posedgeclk or negedge rst_n)

begin

if(!rst_n)

begin

cnt<= 2'd0;

end

else if(cnt_en)

begin

if(ina)

cnt <= cnt+2'd1;

end

else

begin

cnt <=2'd0;

end

end


17、What are the different sources of powerconsumption? Please describe different techniques used to reduce powerconsumption.芯片的功耗分为哪种类型,请描述降低功耗的方式。

 

18、Two modules share one single port ram,please design an Arbiter with following requirements (按要求编写代码):

a)Module A has high priority

b)Basic ram signal: clk, rst_n, wren, addr [7:0], wdata [7:0], rdata [7:0]

c)Ram read access latency is 2 Tclk




19、Implement below RTL logic with DFF andNOR/NAND/INV cells(按要求编写代码):

always@(posedge clk or negedge rst_n) begin

if(!rst_n)

C<=1'b0;

else if (B)

C<=~A;

else;

end

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全部评论
顶一下,觉得能写数字ic的都是高手
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发布于 2022-02-14 19:20
答案呢??
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发布于 2022-03-11 12:18

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