题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
    reg [15:0] d_buff ;
    wire [4:0] buff_1 ;
    wire [4:0] buff_2 ;
    wire [4:0] buff_3 ;
    assign buff_1 = d_buff[3:0] + d_buff[7:4] ;
    assign buff_2 = d_buff[3:0] + d_buff[11:8] ;
    assign buff_3 = d_buff[3:0] + d_buff[15:12] ;
    always @(posedge clk or negedge rst ) begin
        if ( ~rst ) begin 
            d_buff <= 16'd0 ;
        end
        else if (sel == 2'd0 ) begin
            d_buff <= d ;
        end
    end
    
    assign validout = (rst) && (sel!=2'd0) ;
    
    assign out = sel[1] ? (sel[0] ? (buff_3) : buff_2 ) : (sel[0] ? (buff_1) : 5'd0 );
//*************code***********//
endmodule