still do not understand always的并行串行

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    reg[2:0] p;
    reg match1;
    always@(posedge clk or negedge rst_n)begin
        
        if(!rst_n)begin
            match<=0;
            match1<=0;
        end
        else begin
            match<=0;
            casez({a,p,match1})
                5'b00000:p<=3'b001;
                5'b10010:p<=3'b010;
                5'b10100:begin
                    p<=3'b011;
                end
                5'b10110:begin
                    p<=3'b100;
                end
                5'b01000:begin
                    p<=3'b101;
                end
                5'b01010:begin
                    p<=3'b110;
                end
                5'b01100:begin
                    p<=3'b111;
                end
                5'b11110:begin
                    match1<=1;
                    p<=3'b000;
                end
                5'b01110:begin
                    match1<=1;
                    p<=3'b000;
                end
                5'b00001:begin
                    match<=1;
                    match1<=0;
                end
                default:begin
                    if(!a)
                        p<=3'b001;
                    else
                        p<=3'b000;
                end
            endcase
        end
    end
    
  
endmodule