我去这都可以

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
    reg [3:0]p=0;
    always@(posedge clk or negedge rst_n or negedge clk)begin
        if(!rst_n)
            p<=0;
        else begin
            p<=addr*2;
        end
    end
    assign data=p;
endmodule