题解 | #状态机-重叠序列检测#

````timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    //first way:Mooro
   localparam IDLE=0, S1=1, S10=2, S101=3, S1011=4;
    reg [2:0] state, n_state;
    always@(posedge clk or negedge rst)
        if(!rst) state <= IDLE;
        else state <= n_state;
    always@(*)
        case(state)
            IDLE:n_state = data? S1:IDLE;
            S1:  n_state = data? S1:S10;
            S10: n_state = data? S101:IDLE;
            S101:n_state = data? S1011:S10;
            S1011:n_state = data? S1:S10;
        endcase
    always@(posedge clk or negedge rst)
        if(!rst) flag <= 0;
    else if(state==S1011) flag <= 1;
    else flag <= 0;
    //second way：移位寄存器
    reg [3:0] val;
    always@(posedge clk or negedge rst)
        if(!rst) val <= 4'b0; 
        else val <= {val[2:0], data};
    always@(posedge clk or negedge rst)
        if(!rst) flag <= 0;
    else if(val == 4'b1011) flag <= 1;
    else flag <= 0;
    
//*************code***********//
endmodule