题解 | #自动贩售机2#

`timescale 1ns/1ns
module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
    input wire sel,
	
	output reg out1,
	output reg out2,
    output reg out3
);
//*************code***********//
    reg[2:0]state,next_state;
    parameter IDLE=3'd0,S1=3'd1,S2=3'd2,S3=3'd3,S4=3'd4,S5=3'd5,S6=3'd6;
    always@(posedge clk&nbs***bsp;negedge rst)begin
        if(!rst)begin
            state<=IDLE;
        end
        else begin
            state<=next_state;
        end
    end
    always@(*)begin
        case(state)
            IDLE:begin
                if(d1)begin
                    next_state=S1;
                end
                else if(d2)begin
                    next_state=S2;
                end
                else begin
                    next_state=next_state;
                end
            end
            S1:begin
                if(d1)begin
                    next_state=S2;
                end
                else if(d2)begin
                    next_state=S3;
                end
                else begin
                    next_state=next_state;
                end
            end
            S2:begin
                if(d1)begin
                    next_state=S3;
                end
                else if(d2)begin
                    next_state=S4;
                end
                else begin
                    next_state=next_state;
                end
            end
            S3:begin
                if(!sel)begin
                    next_state=IDLE;
                end
                else begin
                    if(d1)begin
                        next_state=S4;
                    end
                    else if(d2)begin
                        next_state=S5;
                    end
                    else begin
                        next_state=next_state;
                    end
                end
            end
            S4:begin
                if(!sel)begin
                    next_state=IDLE;
                end
                else begin
                    if(d1)begin
                        next_state=S5;
                    end
                    else if(d2)begin
                        next_state=S6;
                    end
                    else begin
                        next_state=next_state;
                    end
                end
            end
            default:next_state=IDLE;
        endcase
    end
    always@(posedge clk&nbs***bsp;negedge rst)begin
        if(!rst)begin
            out1<=1'b0;
            out2<=1'b0;
            out3<=1'b0;
        end
        else begin
            if(!sel)begin
                out2<=1'b0;
                if(next_state==S3)begin
                    out1<=1'b1;
                    out3<=1'b0;
                end
                else if(next_state==S4)begin
                    out1<=1'b1;
                    out3<=1'b1;
                end
                else begin
                    out1<=1'b0;
                    out3<=1'b0;
                end
            end
            else begin
                out1<=1'b0;
                if(next_state==S5)begin
                    out2<=1'b1;
                    out3<=1'b0;
                end
                else if(next_state==S6)begin
                    out2<=1'b1;
                    out3<=1'b1;
                end
                else begin
                    out2<=1'b0;
                    out3<=1'b0;
                end
            end
        end
    end

//*************code***********//
endmodule