题解 | #不重叠序列检测#

mealy状态机（能用moore还是用moore吧）：

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
    
    parameter s0=3'd1, s1=3'd2, s2=3'd3, s3=3'd4, s4=3'd5, s5=3'd6, free=3'd7;
    reg[2:0] cnt, c_state, n_state;
    reg match1, not_match1;
    
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n || cnt==3'd5)
            cnt<=3'd0;
        else
            cnt<=cnt+3'd1;
    end
    
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)
            c_state<=s0;
        else
            c_state<=n_state;
    end
    
    always @(*)begin
        case(c_state)
            s0:    n_state=data?free:s1;
            s1:    n_state=data?s2:free;
            s2:    n_state=data?s3:free;
            s3:    n_state=data?s4:free;
            s4:    n_state=data?free:s5;
            s5:    n_state=data?free:s0;
            free:    n_state=((cnt==3'd5)&&(~data))?s1:free;
            default:    n_state=s0;
        endcase
    end

    always@(posedge clk or negedge rst_n)begin
      if(!rst_n)begin
         match<=0;
         not_match<=0;
       end
       else if(cnt==3'd5)begin
           if(c_state==s5 && ~data)begin 
                   match<=1;
                   not_match<=0;
               end
               else begin
                   match<=0;
                   not_match<=1;
               end
        end
        else begin
         match<=0;
         not_match<=0;
       end
    end

endmodule