题解 | #输入序列不连续的序列检测#

注意点： 1.ready_a信号是寄存器类型，有复位，不是恒高电平。（和计数条件有关） 2.data_b无效时保持结果不变。

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
    //defination
    reg [2 : 0] cnt;
    wire add_cnt;
    wire end_cnt;
    reg [5 : 0] temp_b;
    
    
    //output 
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) ready_a <= 'd0;
        else ready_a <= 1'b1;
    end
    
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) temp_b <= 'd0;
        else if(ready_a && valid_a) temp_b <= {data_a, temp_b[5 : 1]};
    end
    
    assign add_cnt = ready_a && valid_a;
    assign end_cnt = add_cnt && (cnt == 5);
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) cnt <= 'd0;
        else if(end_cnt) cnt <= 'd0;
        else if(add_cnt) cnt <= cnt + 1'b1;
    end
    
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) valid_b <= 'd0;
        else if(end_cnt) valid_b <= 1'b1;
        else valid_b <= 1'b0;
    end
    
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) data_b <= 'd0;
        else if(end_cnt) data_b <= {data_a, temp_b[5 : 1]}; 
    end
endmodule