题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    reg [8:0] val;
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            val <= 9'b0;
        end else begin
            val <= {val[7:0],a};
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            match <= 1'b0;
        end else begin
            casex (val)
                9'b011xxx110 : match <= 1'b1;
                default : match <= 1'b0;
            endcase
        end
    end
  
endmodule