题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
    wire [7:0] m,n;
    compare u1 ( .x(a), .y(b), .clk(clk), .rst_n(rst_n), .z(m) );
    compare u2 ( .x(b), .y(c), .clk(clk), .rst_n(rst_n), .z(n) );
    compare u3 ( .x(m), .y(n), .clk(clk), .rst_n(rst_n), .z(d) );

endmodule

module compare (
    input clk,
    input rst_n,
    input [7:0] x,y,
    output reg [7:0] z );
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            z <= 8'b0;
        end else if (x <= y) begin
            z <= x;
        end else begin
            z <= y;
        end
    end
endmodule