题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg tff1;
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            q <= 0;
            tff1 <= 0;
        end else begin
            if (tff1) begin
                q <= ~q;
            end else begin
                q <= q;
            end
            if (data) begin
                tff1 <= ~tff1;
            end else begin
                tff1 <= tff1;
            end
            
        end
    end

//*************code***********//
endmodule