`timescale 1ns/1ns module edge_detect( input clk, input rst_n, input a, output reg rise, output reg down ); reg out1; always @(posedge clk or negedge rst_n) if(!rst_n) out1 <= 0; else out1 <= a; always @(posedge clk or negedge rst_n) if(!rst_n)begin rise ...