`timescale 1ns/1ns module lca_4( input [3:0] A_in , input [3:0] B_in , input C_1 , output wire CO , output wire [3:0] S ); reg [3:0] G, P, C; reg [3:0] Si; integer i; always @(*) begin // 初始化 G = 4'b0; P...