题解 | ROM的简单实现
`timescale 1ns/1ns module rom( input clk, input rst_n, input [7:0]addr, output [3:0]data ); reg [3:0] mem [7:0]; assign data = mem[addr]; integer i; always@(posedge clk or negedge rst_n) if (!rst_n) for (i = 0; i < 8; i = i + 1) mem[i] <= i * 4'd2; else for (i = 0; i < 8; i = i + 1) mem[i] <= mem[i]; endmodule