题解 | 边沿检测
`timescale 1ns/1ns module edge_detect( input clk, input rst_n, input a, output reg rise, output reg down ); reg ar; always @(posedge clk or negedge rst_n) begin if (~rst_n) begin ar <= 0; end else begin ar <=a; end end always @(posedge clk or negedge rst_n) begin if (~rst_n) begin rise <= 1'b0; down <= 1'b0; end else if (a & ~ar) begin rise <= 1'b1; end else if (~a & ar) begin down <= 1'b1; end else begin rise <= 1'b0; down <= 1'b0; end end endmodule