题解 | 根据状态转移图实现时序电路

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

parameter A=0,B=1,Cx=2,D=3;
reg [1:0] state_c,state_n;
reg Y0;
 always @(posedge clk or negedge rst_n) begin
       if (~rst_n) begin
          state_c <= A;
       end else begin
          state_c <= state_n;
       end
    end

 always @(*) begin
        case (state_c)
            A: begin
                if (~C) begin
                    state_n = state_c;
                    Y0      = 1'b0;
                end else begin
                    state_n = B;
                    Y0      = 1'b0;
                end
            end
            B: begin
                if (C) begin
                    state_n = state_c;
                    Y0      = 1'b0;
                end else begin
                    state_n = D;
                    Y0      = 1'b0;
                end
            end
            Cx: begin
                if (C) begin
                    state_n = state_c;
                    Y0      = 1'b1;
                end else begin
                    state_n = A;
                    Y0      = 1'b0;
                end
            end
            D: begin
                if (~C) begin
                    state_n = state_c;
                    Y0      = 1'b1;
                end else begin
                    state_n = Cx;
                    Y0      = 1'b1;
                end
            end
            default: begin
                state_n = state_c;
            end
        endcase
    end

assign Y = Y0;
endmodule