题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
reg r_Y;
//三段状态机
localparam P_s0=2'b00,P_s1=2'b01,P_s2=2'b10,P_s3=2'b11;

reg [1:0]r_st_current,r_st_next;

always@(posedge clk, negedge rst_n)begin
    if(!rst_n)
        r_st_current <= 0;
    else 
        r_st_current <= r_st_next;
end

always@(*)begin
    if(!rst_n)
        r_st_next <= P_s0;
    else begin
        case(r_st_current)
        P_s0:r_st_next <= C?P_s1:P_s0;
        P_s1:r_st_next <= C?P_s1:P_s3;
        P_s2:r_st_next <= C?P_s2:P_s0;
        P_s3:r_st_next <= C?P_s2:P_s3;
        default:r_st_next <= P_s0;
    
        endcase
        end
end

always@(*)begin
    if(!rst_n)
        r_Y <= 0;
    else begin
        case(r_st_current)
        P_s0:r_Y <= C?0:0;
        P_s1:r_Y <= C?0:0;
        P_s2:r_Y <= C?1:0;
        P_s3:r_Y <= C?1:1;
        default:r_Y <= 0;
    
        endcase
        end
end
assign Y = r_Y;

endmodule