题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0] ri_data;

always@(posedge clk, negedge rst)begin
    if(!rst)
        ri_data <= 0;
    else if(sel == 0)
        ri_data <= d;
    else
        ri_data <= ri_data;
end

always@(posedge clk , negedge rst)begin
    if(!rst)
        validout <= 0;
    else if(sel == 0 )
        validout <= 0;
    else 
        validout <= 1;


end

always@(posedge clk , negedge rst)begin
    if(!rst)
        out <= 0;
    else
        case(sel)
            0:out <= 0;
            1:out <=ri_data[3:0]+ri_data[7:4]; 
            2: out<=ri_data[3:0]+ri_data[11:8];
            3: out<=ri_data[3:0]+ri_data[15:12];
            default:out <= 0;
        endcase


end

//*************code***********//
endmodule