题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
reg [3:0] reg_data[7:0];
genvar i;
generate for(i = 0;i < 8;i = i + 1)
	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)begin
			reg_data[i] <= i<<1;
		end
	end
endgenerate
assign data = reg_data[addr];

endmodule