题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//

reg         validout;
reg [4:0]   out;
reg [15:0]r_d;
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        validout <= 'd0; 
        out <= 'd0;
         r_d <='d0;
    end
    else begin 
        case(sel)
            'd0 : begin  validout <= 'd0;  out <= 'd0; r_d <= d;end
            'd1 : begin  validout <= 'd1;  out <=  r_d[3:0]+ r_d[7:4];  end
            'd2 : begin  validout <= 'd1;  out <=  r_d[3:0]+ r_d[11:8]; end
            'd3 : begin  validout <= 'd1;  out <=  r_d[3:0]+ r_d[15:12];end
            default:begin  validout <= 'd0;  out <= 'd0; end
        endcase

    end


end
//*************code***********//
endmodule