题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    reg clk_out2,
    output    reg clk_out4,
    output    reg clk_out8
    );
//*************code***********//

reg [2:0] cnt;

always @(posedge clk_in or negedge rst)begin
    if(!rst)begin
        cnt <= 3'd0;
    end
    else if(cnt == 3'd7) begin
        cnt <= 0;
    end
    else begin
        cnt <= cnt + 1'd1;
    end
end

always @(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_out2    <= 1'b0;
        clk_out4    <= 1'b0;
        clk_out8    <= 1'b0;
    end
    else begin
        clk_out2    <= !cnt[0];
        clk_out4    <= !cnt[1];
        clk_out8    <= !cnt[2];
    end
end 




//*************code***********//
endmodule