题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
);
parameter IDLE = 4'b1111;//设置了一个启示状态，用于在一开始进入循环中

parameter SR0 = 4'b0000;
parameter SR1 = 4'b0001;
parameter SR2 = 4'b0010;
parameter SR3 = 4'b0011;
parameter SR4 = 4'b0100;
parameter SR5 = 4'b0101;

parameter SW0 = 4'b1000;
parameter SW1 = 4'b1001;
parameter SW2 = 4'b1010;
parameter SW3 = 4'b1011;
parameter SW4 = 4'b1100;
parameter SW5 = 4'b1101;

reg [3:0] state;
reg [3:0] next_state;

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    state <= IDLE;
  else
    state <= next_state;
end

always@(*)begin
  case(state)
    IDLE:next_state = (data == 1'b0)?SR0:SW0;
    SR0:next_state = (data == 1'b1)?SR1:SW1;
    SR1:next_state = (data == 1'b1)?SR2:SW2;
    SR2:next_state = (data == 1'b1)?SR3:SW3;
    SR3:next_state = (data == 1'b0)?SR4:SW4;
    SR4:next_state = (data == 1'b0)?SR5:SW5;
    SR5:next_state = (data == 1'b0)?SR0:SW0;
    SW0:next_state = SW1;
    SW1:next_state = SW2;
    SW2:next_state = SW3;
    SW3:next_state = SW4;
    SW4:next_state = SW5;
    SW5:next_state = (data == 1'b0)?SR0:SW0;
	default:next_state = IDLE;
  endcase
end

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)begin
    match <= 1'b0;
	not_match <= 1'b0;
  end
  else begin
    match <= (next_state == SR5)?1'b1:1'b0;//按照时序图的要求，在序列出现后的下一个时钟周期拉高标识
	not_match <= (next_state == SW5)?1'b1:1'b0;
  end
end

endmodule