题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

reg data_en_r1;
reg [3:0] data_in_r1;

reg data_en_rb1;
reg data_en_rb2;
reg [3:0] data_in_rb1;

always @(posedge clk_a or negedge arstn)begin
	if(!arstn)begin
		data_en_r1	<= 1'b0;
	end
	else begin
		data_en_r1	<= data_en;
	end
end

always @(posedge clk_a or negedge arstn)begin
	if(!arstn)begin
		data_in_r1	<= 4'b0;
	end
	else begin
		data_in_r1	<= data_in;
	end
end

always @(posedge clk_b or negedge brstn)begin
	if(!brstn)begin
		data_en_rb1	<= 1'b0;
		data_en_rb2	<= 1'b0;
	end
	else begin
		data_en_rb1	<= data_en_r1;
		data_en_rb2	<= data_en_rb1;
	end
end

always @(posedge clk_b or negedge brstn)begin
	if(!brstn)begin
		dataout		<= 4'b0;
		data_in_rb1	<= 4'b0;
	end
	else begin
		data_in_rb1	<= data_in_r1;
		if(data_en_rb2)begin
			dataout	<= data_in_rb1;
		end
	end
end


endmodule