题解 | #不重叠序列检测#

题目中reg变量再always块中赋值

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

//PARAMETER     defined
parameter IDLE  =  8'b00000001;
parameter S1    =  8'b00000010;
parameter S2    =  8'b00000100;
parameter S3    =  8'b00001000;
parameter S4    =  8'b00010000;
parameter S5    =  8'b00100000;
parameter S6    =  8'b01000000;

//reg defined 
reg [7:0]       curr_state;
reg [7:0]       next_state;
reg [5:0]      match_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        curr_state <= IDLE;
    end
    else begin
        curr_state <= next_state;
    end
end

always @( *) begin
    case (curr_state)
    IDLE:   next_state <= S1;

    S1:begin
            next_state = S2;
            if (!data) begin
                match_reg[5] = 1'd1;
            end
            else
                match_reg[5] = 1'd0;
        end
    S2: begin
        next_state <= S3;
            if (data) begin
                match_reg[4] = 1'd1;
            end
            else
                match_reg[4] = 1'd0;
    end
    S3: begin
        next_state <= S4;
            if (data) begin
                match_reg[3] = 1'd1;
            end
            else
                match_reg[3] = 1'd0;
    end
    S4: begin
        next_state <= S5;
            if (data) begin
                match_reg[2] = 1'd1;
            end
            else
                match_reg[2] = 1'd0;
    end
    S5: begin
        next_state <= S6;
            if (!data) begin
                match_reg[1] = 1'd1;
            end
            else
                match_reg[1] = 1'd0;
    end
    S6: begin
        next_state = S1;
            if (!data) begin
                match_reg[0] = 1'd1;
            end
            else
                match_reg[0] = 1'd0;
    end
    endcase
end

always @(*) begin
    if (curr_state == S6 ) begin
        if (match_reg == 6'b111111) begin
            match = 1'b1;
            not_match = 1'b0;
        end
        else begin
            match = 1'b0;
            not_match = 1'b1;
        end
    end
    else begin
        match = 1'b0;
        not_match = 1'b0;
    end
end



endmodule

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