题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

parameter IDLE  =  9'b000000001;
parameter S1    =  9'b000000010;
parameter S2    =  9'b000000100;
parameter S3    =  9'b000001000;
parameter S4    =  9'b000010000;
parameter S5    =  9'b000100000;
parameter S6    =  9'b001000000;
parameter S7    =  9'b010000000;
parameter S8    =  9'b100000000;

reg [8:0]       curr_state;
reg [8:0]       next_state;

//fsm
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        curr_state <= IDLE;
    end
    else
        curr_state <= next_state;
end

always @( *) begin
    case (curr_state)
        IDLE: next_state = (~a)? S1 : IDLE;
        S1:next_state = (a)? S2 : S1;
        S2:next_state = (a)? S3 : S1;
        S3:next_state = (a)? S4 : S1;
        S4:next_state = (~a)? S5 : IDLE;
        S5:next_state = (~a)? S6 : S2;
        S6:next_state = (~a)? S7 : S2;
        S7:next_state = (a)? S8 : S1;
        S8:next_state = (a)? S1 : IDLE;
        default : next_state = curr_state;
    endcase
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        match <= 1'b0;
    end
    else
        if (curr_state == S8) begin
            match <= 1'b1;
        end
        else
            match <= 1'b0;
end

endmodule