题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
reg [6:0] sys_cnt;
reg div_flag;
reg [3:0] cnt;
reg clk_out_r;
always @ (posedge clk_in or negedge rst) begin
    if(!rst) begin
        sys_cnt <= 7'b0;
    end
    else if(sys_cnt == M_N - 1'b1) begin
        sys_cnt <= 7'b0;
    end
    else begin
        sys_cnt <= sys_cnt + 1'b1;
    end
end
always @ (posedge clk_in or negedge rst) begin
    if(!rst) begin
        div_flag <= 1'b0;
    end
    else begin
        div_flag <= (sys_cnt <= c89 - 1'b1) ? 1'b0 : 1'b1;
    end
end
always @ (posedge clk_in or negedge rst) begin
    if(!rst) begin
        cnt <= 3'b0;
    end
    else if(!div_flag) begin
        if(cnt == div_e - 1'b1) begin
            cnt <= 3'b0;
        end
        else begin
            cnt <= cnt + 1'b1;
        end
    end
    else begin
        if(cnt == div_o - 1'b1) begin
            cnt <= 3'b0;
        end
        else begin
            cnt <= cnt + 1'b1;
        end
    end
end
always @ (posedge clk_in or negedge rst) begin
    if(!rst) begin
        clk_out_r <= 1'b0;
    end
    else if(!div_flag) begin
        clk_out_r <= (cnt <= 4'b0011);
    end
    else begin
        clk_out_r <= (cnt <= 4'b0011);
    end
end
assign clk_out = clk_out_r;
//*************code***********//
endmodule